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wse128k16-xxx 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary* white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 128kx16 sram/eeprom module features access times of 35ns (sram) and 150ns (eeprom) access times of 45ns (sram) and 120ns (eeprom) access times of 70ns (sram) and 300ns (eeprom) packaging ? 66 pin, pga type, 1.075" square hip, hermetic ceramic hip (h1) (package 400) ? 68 lead, hermetic cqfp (g2t), 22mm (0.880") square (package 509). designed to ? t jedec 68 lead 0.990" cqfj footprint (figure 2) 128kx16 sram 128kx16 eeprom organized as 128kx16 of sram and 128kx16 of eeprom memory with separate data buses both blocks of memory are user con? gurable as 256kx8 low power cmos block diagram pin description ed 0-15 eeprom data inputs/outputs sd 0-15 sram data inputs/outputs a 0-16 address inputs swe# 1-2 sram write enable scs# 1-2 sram chip selects oe# output enable v cc power supply gnd ground nc not connected ewe# 1-2 eeprom write enable ecs# 1-2 eeprom chip select top view figure 1 C wse128k16-xh1x pin configuration commercial, industrial and military temperature ranges ttl compatible inputs and outputs built-in decoupling caps and multiple ground pins for low noise operation weight - 13 grams typical eeprom memory features write endurance 10,000 cycles data retention at 25c, 10 years low power cmos operation automatic page write operation page write cycle time 10ms max. data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs * this product is under development, is not quali? ed or characterized and is subject to change without notice. sd 8 sd 9 sd 10 a 13 a 14 a 15 a 16 nc sd 0 sd 1 sd 2 11 22 33 44 55 66 11223 344556 ed 8 ed 9 ed 10 a 6 a 7 nc a 8 a 9 ed 0 ed 1 ed 2 sd 15 sd 14 sd 13 sd 12 oe# nc swe# 1 sd 7 sd 6 sd 5 sd 4 swe 2 # scs 2 # gnd sd 11 a 10 a 11 a 12 v cc scs 1 # nc sd 3 ed 15 ed 14 ed 13 ed 12 a 0 a 1 a 2 ed 7 ed 6 ed 5 ed 5 v cc ecs 2 # ewe 2 # ed 11 a 3 a 4 a 5 ewe 1 # ecs 1 # gnd ed 3 ewe 1 # ecs 1 # ewe 2 # ecs 2 # swe 2 # scs 2 # 128k x 8 sram 8 sd 0-7 128k x 8 sram 8 sd 8-15 128k x 8 eeprom 8 ed 0-7 128k x 8 eeprom 8 ed 8-15 a 0-16 oe# swe 1 # scs 1 #
wse128k16-xxx 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 top view figure 2 wse128k16-xg2tx pin configuration block diagram pin description ed 0-15 eeprom data inputs/outputs sd 0-15 sram data inputs/outputs a 0-16 address inputs swe# 1-2 sram write enable scs# 1-2 sram chip selects oe# output enable v cc power supply gnd ground nc not connected ewe# 1-2 eeprom write enable ecs# 1-2 eeprom chip select the wedc 68 lead g2t cqfp ? lls the same ? t and function as the jedec 68 lead cqfj or 68 plcc. but the g2t has the tce and lead inspection advantage of the cqfp form. ewe 1 # ecs 1 # ewe 2 # ecs 2 # swe 2 # scs 2 # 128k x 8 sram 8 sd 0-7 128k x 8 sram 8 sd 8-15 128k x 8 eeprom 8 ed 0-7 128k x 8 eeprom 8 ed 8-15 a 0-16 oe# swe 1 # scs 1 # 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 sd 0 sd 1 sd 2 sd 3 sd 4 sd 5 sd 6 sd 7 gnd sd 8 sd 9 sd 10 sd 11 sd 12 sd 13 sd 14 sd 15 v cc a 11 a 12 a 13 a 14 a 15 a 16 scs 1 # oe# scs 2 # nc swe 2 # ewe 1 # ewe 2 # nc nc nc ed 0 ed 1 ed 2 ed 3 ed 4 ed 5 ed 6 ed 7 gnd ed 8 ed 9 ed 10 ed 11 ed 12 ed 13 ed 14 ed 15 nc a 0 a 1 a 2 a 3 a 4 a 5 ecs 1 # gnd ecs 2 # swe 1 # a 6 a 7 a 8 a 9 a 10 v cc 0.940"
wse128k16-xxx 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.3 +0.8 v operating temp. (mil.) t a -55 +125 c eeprom truth table cs# oe# we# mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write inhibit xlx sram truth table scs# oe# swe# mode data i/o power h x x standby high z standby l l h read data out active l h h read high z active l x l write data in active dc characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo scs# = v ih , oe# = v ih , v out = gnd to v cc 10 a sram operating supply current x 16 mode i cc x16 scs# = v il , oe# = ecs# = v ih , f = 5mhz, v cc = 5.5 360 ma standby current isb ecs# = scs# = v ih , oe# = v ih , f = 5mhz, v cc = 5.5 31.2 ma sram output low voltage (35 to 45ns) v ol i ol = 8.0ma, v cc = 4.5 0.4 v (70ns) v ol i ol = 2.1ma, v cc = 4.5 0.4 v sram output high voltage (35 to 45ns) v oh i oh = -4.0ma, v cc = 4.5 2.4 v (70ns) v oh i oh = -1ma, v cc = 4.5 2.4 v eeprom operating supply current x 16 mode i cc1 ecs# = v il , oe# = scs# = v ih 155 ma eeprom output low voltage v ol i ol = 2.1 ma, v cc = 4.5v 0.45 v eeprom output high voltage v oh1 i oh = 400 a, v cc = 4.5v 2.4 v notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (@ 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. dc test conditions: v il = 0.3v, v ih = v cc - 0.3v absolute maximum ratings parameter symbol min max unit operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 v cc +0.5 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v capacitance t a = +25c parameter symbol conditions max unit oe# capacitance c oe v in = 0 v, f = 1.0 mhz 50 pf we# 1-4 capacitance hip (pga) c we v in = 0 v, f = 1.0 mhz 20 pf cqfp g2t 20 cs# 1-4 capacitance c cs v in = 0 v, f = 1.0 mhz 20 pf data i/o capacitance c i/o v i/o = 0 v, f = 1.0 mhz 20 pf address input capacitance c ad v in = 0 v, f = 1.0 mhz 50 pf this parameter is guaranteed by design but not tested.
wse128k16-xxx 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 figure 3 C ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. sram ac characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c parameter read cycle symbol -35 -45 -70 units min max min max min max read cycle time t rc 35 45 70 ns address access time t aa 35 45 70 ns output hold from address change t oh 005ns chip select access time t acs 35 45 70 ns output enable to output valid t oe 20 25 35 ns chip select to output in low z t clz1 335ns output enable to output in low z t olz1 005ns chip disable to output in high z t chz1 20 20 25 ns output disable to output in high z t ohz1 20 20 25 ns 1. this parameter is guaranteed by design but not tested. sram ac characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c parameter write cycle symbol -35 -45 -70 units min max min max min max write cycle time t wc 35 45 70 ns chip select to end of write t cw 25 30 60 ns address valid to end of write t aw 25 30 60 ns data valid to end of write t dw 20 25 30 ns write pulse width t wp 25 30 50 ns address setup time t as 005ns address hold time t ah 005ns output active from end of write t ow1 445ns write enable to output in high z t whz1 20 25 25 ns data hold time t dh 000ns 1. this parameter is guaranteed by design but not tested. i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh
wse128k16-xxx 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 figure 4 C sram read cycles address sram data i/o previous data valid data valid t rc t aa read cycle 1, (scs# = oe# = v il , swe# = v ih ) t oh address scs# soe# sram data i/o t rc t aa t acs t clz t oe t olz t chz t ohz high impedance read cycel 2, (swe# = v ih ) data valid figure 5 C sram write cycle swe# controlled address scs# swe# sram data i/o t wc t aw t cw t ah t wp t ow t as t whz t dw t dh data valid write cycle 1, swe# controlled figure 6 C sram write cycel scs# controlled address scs# swe# sram data i/o t wc t aw t cw t as t ah t dh t dw t wp data valid write cycle 2, scs# controlled
wse128k16-xxx 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 eeprom write a write cycle is initiated when oe# is high and a low pulse is on ewe# or ecs# with ecs# or ewe# low. the address is latched on the falling edge of ecs# or ewe# whichever occurs last. the data is latched by the rising edge of ecs# or ewe#, whichever occurs ? rst. a byte write operation will automatically continue to completion. write cycle timing figures 7 and 8 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the ecs# line low. write enable consists of setting the ewe# line low. the write cycle begins when the last of either ecs# or ewe# goes low. the ewe# line transition from high to low also initiates an internal 150 sec delay timer to permit page mode operation. each subsequent ewe# transition from high to low that occurs before the completion of the 150 sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. eeprom ac write characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c write cycle parameter symbol min max unit write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns write pulse width (ewe# or ecs#) t wp 150 ns chip select set-up time t cs 0ns address hold time t ah 100 ns data hold time t dh 10 ns chip select hold time t csh 0ns data set-up time t ds 100 ns output enable set-up time t oes 10 ns output enable hold time t oeh 10 ns write pulse width high t wph 50 ns
wse128k16-xxx 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 figure 7 C eeprom write waveforms ewe# controlled figure 8 C eeprom write waveforms ecs# controlled t dh t wph t wp t csh t oeh t ah t oes t as t cs oe# address ecs# 1-2 ewe# 1-2 eeprom data in t wc t ds t dh t wph t wp t csh t oeh t ah t oes t as t cs oe# address ecs# 1-2 ewe# 1-2 eeprom data in t ds t wc
wse128k16-xxx 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 figure 9 C eeprom read waveforms eeprom read the wse128k16-xxx eeprom stores data at the memory location determined by the address pins. when ecs# and oe# are low and ewe# is high, this data is present on the outputs. when ecs# and oe# are high, the outputs are in a high impedance state. this two line control prevents bus contention. note: oe# may be delayed up to t acs - t oe after the falling edge of ecs# without impact on t oe or by t acc - t oe after an address change without impact on t acc . eeprom ac read characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c read cycle parameter symbol -120 -150 -300 unit min max min max min max read cycle time t rc 120 150 300 ns address access time t acc 120 150 300 ns chip select access time t acs 120 150 300 ns output hold from add. change, oe# or ecs# t oh 000ns output enable to output valid t oe 050055085ns chip select or oe# to high z output t df 70 70 70 ns t oh address ecs# 1-2 oe# eeprom data output t df t acc t rc t oe t acs output valid address valid high z
wse128k16-xxx 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 eeprom data polling the wse128k16-xxx offers a data polling feature for the eeprom which allows a faster method of writing to the device. figure 11 shows the timing diagram for this function. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on d7 (for each chip.) once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. figure 10 C eeprom data polling waveforms eeprom data polling characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c parameter symbol min max unit data hold time t dh 10 ns oe# hold time t oeh 10 ns oe# to output valid t oe 55 ns write recovery time t wr 0ns ewe# 1-2 ecs# 1-2 oe# ed 7 address t oeh t dh t oe t wr high z
wse128k16-xxx 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 eeprom page write operation the wse128k16-xxx has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. successive bytes may be loaded in the same manner after the ? rst data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least signi? cant address lines from a0 through a6 at each write cycle. in this manner a page of up to 128 bytes can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. figure 11 C eeprom page mode write waveforms eeprom page write characteristics v cc = 5.0v, gnd = 0v, -55c t a +125c page mode write characteristics parameter symbol min max unit write cycle time, typ = 6ms t wc 10 ms address set-up time t as 0ns address hold time (1) t ah 100 ns data set-up time t ds 100 ns data hold time t dh 10 ns write pulse width t wp 150 ns byte load cycle time t blc 150 s write pulse width high t wph 50 ns note: 1. page address must remain valid for duration of write cycle. byte 0 byte 1 byte 2 byte 3 va l i d data valid address t wc t bl c t wph t wp byte 127 t ds t dh t as t ah oe# ecs# 1-2 ewe# 1-2 address eeprom data after the 150s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed.
wse128k16-xxx 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address figure 12 C eeprom software data protection enable algorithm (1) writes enabled (2) notes: 1. data format: ed7 - ed0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. enter data protect state
wse128k16-xxx 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 eeprom hardware data protection these features protect against inadvertent writes to the wse128k16-xxx. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5 msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe# low and either ecs# or ewe# high inhibits write cycles. d) noise ? lter pulses of <8ns (typ) on ewe# or ecs# will not initiate a write cycle. eeprom software data protection a software write protection feature may be enabled or disabled by the user. when shipped by wedc, the wse128k16-xxx has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device, however, for the duration of twc. the write protection feature can be disabled by a six byte write sequence of speci? c data to speci? c locations. power transitions will not reset the software write protection. each 128k byte block of the eeprom has independent write protection. one or more blocks may be enabled and the rest disabled in any combination. the software write protection guards against inadvertent writes during power transitions, or unauthorized modi? cation using a prom programmer. figure 13 C eeprom software data protection disable algorithm (1) exit data (3) protect state notes: 1. data format: ed7 - ed0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address (4) load last byte to last address
wse128k16-xxx 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 package 400: 66 pin, pga type, ceramic hex-in-line package, hip (h1) all linear dimensions are millimeters and parenthetically in inches pin 1 identifier square pad on bottom 27.3 (1.075) 0.25 (0.010) sq 3.81 (0.150) 0.13 (0.005) 1.42 (0.056) 0.13 (0.005) 0.76 (0.030) 0.13 (0.005) 1.27 (0.050) typ dia 25.4 (1.0) typ 0.46 (0.018) 0.05 (0.002) dia 4.34 (0.171) max 2.54 (0.100) typ 15.24 (0.600) typ 25.4 (1.0) typ
wse128k16-xxx 14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 0.38 (0.015) 0.05 (0.002) 0.27 (0.011) 0.04 (0.002) 25.15 (0.990) 0.26 (0.010) sq 1.27 (0.050) typ 24.03 (0.946) 0.26 (0.010) 22.36 (0.880) 0.26 (0.010) sq 20.3 (0.800) ref 4.57 (0.180) max 0.19 (0.007) 0.06 (0.002) 23.87 (0.940) ref 1.0 (0.040) 0.127 (0.005) 0.25 (0.010) ref 1 / 7 r 0.25 (0.010) detail a see detail "a" pin 1 0.940" typ package 509: 68 lead, ceramic quad flat pack, cqfp (g2t) all linear dimensions are millimeters and parenthetically in inches the wedc 68 lead g2t cqfp ? lls the same ? t and function as the jedec 68 lead cqfj or 68 plcc. but the g2t has the tce and lead inspection advantage of the cqfp form.
wse128k16-xxx 15 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs preliminary white electronic designs corp. reserves the right to change products or speci? cations without notice. march 2005 rev. 3 ordering information lead finish: blank = gold plated leads a = solder dip leads device grade: m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: h1 = 1.075" sq. ceramic hex-in-line package, hip (package 400) g2t = 22.4mm ceramic quad flat pack, cqfp (package 509) access time (ns) 35 = 35ns sram and 150ns eeprom 42 = 45ns sram and 120ns eeprom 73 = 70ns sram and 300ns eeprom organization, 128k x 16 eeprom sram white electronic designs corp. w s e 128k16 - xxx x x x

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